The present invention relates to a semiconductor device and to a method of manufacturing the sane; and, more particularly, the invention relates to a technique that can effectively be applied to the manufacture of a semiconductor device, including a flattening process utilizing a CMP (Chemical Mechanical Polishing) method.
Trench isolation is one of the isolation methods employed for electrically isolating adjacent semiconductor elements. In a typical trench isolation fabrication process, grooves are provided on a semiconductor substrate, which grooves become an element isolation region, and these grooves are filled with insulation films.
Trench isolation is formed, for example, using the following method. First, grooves are formed to a depth, for example, of about 0.4 μm in the element isolation region of the semiconductor substrate using a dry etching method; and, thereafter, a first insulation film is formed to a thickness, for example, of about 20 nm at the surface where the semiconductor substrate is exposed by carrying out a thermal oxidation process on the semiconductor substrate. Thereafter, a second insulation film is deposited on the semiconductor substrate to fill the inside of the grooves; and, then, the trench isolation is formed by removing the portion of the second insulation film at the outside side of the grooves and leaving the portion of the second insulation film only inside of the grooves, through polishing of the surface of this second insulation film, for example, using the CMP method.
When the width of the element isolation region becomes relatively large, the polishing rate of the second insulation film becomes high in the local area during the CMP process, and, thereby, a so-called dishing phenomenon is easily generated, whereby a “recess” is produced at the central area of the grooves. However, several methods have been proposed to improve the flatness at the surface of the second insulation film in the element isolation region by controlling the dishing phenomenon. A method of providing a dummy pattern is one of such methods.
For example, the Japanese Patent Application Laid-Open No. Hei 10(1998)-92921, corresponding to the U.S. Pat. No. 5,885,856, discloses a method in which each dummy structure is placed in a non-active device area to cause the occupation density in the non-active device area to be equal to that of the active device area, and, thereby, the polishing rate is equalized for the entire part of the semiconductor substrate surface.
Moreover, the inventors of the present invention have considered a method of placing the dummy patterns in a regular manner. The technique explained below has been considered by the inventors of the present invention and its outline is as follows.
FIG. 28 shows a first dummy pattern placing method which the inventors of the present invention have considered.
A plurality of dummy patterns DPA1 are regularly placed in a dummy region (region outside of the frame indicated by the broken line in the figure) FA, where semiconductor elements are not formed, outside of the element forming region (region within the frame of broken line in the figure) DA, where the semiconductor elements are formed. A plurality of dummy patterns DPA1 are formed to be equal in shape and size, and these dummy patterns are extensively placed with the same interval in the dummy region FA.
The element forming region DA and dummy region FA, outside of the active region AC, form element isolation region IS, and a trench isolation is usually formed in the entire part of this isolation region IS. Therefore, this method for regularly placing the dummy patterns has the inherent problem that the dishing phenomenon is easily generated during the CMP process, particularly in the dummy region FA, which is isolated from the active region AC. However, it is now possible to prevent such dishing phenomenon in the dummy region FA by placing a plurality of dummy patterns DP1 therein, whereby the flatness at the surface of the embedding insulation film in the dummy region FA can be improved.
FIG. 29 shows a second dummy pattern placing method which the inventors of the present invention have discussed. Like the method illustrated in FIG. 28, a plurality of dummy patterns DPA2 are regularly placed in the dummy region FA, where the semiconductor elements are not formed, outside of the element forming region DA, where the semiconductor elements are formed, and, thereby, the dishing in the dummy region FA can be prevented. The size of the dummy patterns DPA2 is smaller than the size of the dummy patterns DPA1 and the dummy patterns DPA2 can be placed up to the dummy region FA near the boundary BL (indicated by the frame line in the figure) between the element forming region DA and dummy region FA.